Leakage current detection device and nonvolatile memory device having the same

ABSTRACT

A leakage current detection device includes a test detection circuit, a reference detection circuit, a comparator, and a latch circuit. The test detection circuit is coupled between a test node and a test line, provides a voltage to the test node to charge the test line, floats the test node and the test line, and decreases a voltage of the test node based on leakage current of the test line. The reference detection circuit is coupled between a reference node and a reference line, provides the voltage to the reference node to charge the reference line, floats the reference node and the reference line, and decreases a voltage of the reference node based on self-discharge of the reference line. The comparator outputs a comparison signal by comparing voltages of the test node and the reference node. The latch circuit latches the comparison signal to output a test result signal.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority under 35 USC § 119 to Korean PatentApplication No. 10-2014-0089350, filed on Jul. 15, 2014 in the KoreanIntellectual Property Office (KIPO), the contents of which are hereinincorporated by reference in their entirety.

BACKGROUND

1. Technical Field

Example embodiments relate to a nonvolatile memory device, and moreparticularly to a leakage current detection device and a nonvolatilememory device including the leakage current detection device.

2. Description of the Related Art

Memory devices can be broadly classified into two groups based onwhether they retain stored data when disconnected from power. Thesegroups include volatile memory devices, which lose stored data whendisconnected from power, and nonvolatile memory devices, which retainstored data when disconnected from power. Examples of volatile memorydevices include dynamic random access memory (DRAM), and static randomaccess memory (SRAM), and examples of nonvolatile memory devices includeelectrically erasable and programmable read only memory (EEPROM),phase-change random access memory (PRAM), resistance random accessmemory (RRAM), and magnetic random access memory (MRAM).

EEPROM is one of the more common forms of nonvolatile memory in usetoday due to its ability to be efficiently programmed, read, and erased.Flash EEPROM (hereafter, “flash memory”), for instance, can be found ina wide range of modern electronic devices, including solid state drives,mobile phones, digital cameras, and many others. Memory cells includedin flash memory devices are coupled to drive lines. Flash memory devicesperform program, read, and erase operations on the memory cells byapplying drive signals to the drive lines.

If a drive line has a defect such that a leakage current flows from thedrive line, program, read, and erase operations may not be performedcorrectly on memory cells coupled to the drive line having a defect.Therefore, data stored in the memory cells coupled to the drive linehaving a defect may be lost.

SUMMARY

Some example embodiments are directed to a leakage current detectiondevice that effectively detects a leakage current flowing from a driveline coupled to a memory cell array of a nonvolatile memory device.

Some example embodiments are directed to a nonvolatile memory deviceincluding the leakage current detection device.

According to example embodiments, a leakage current detection deviceincludes a test detection circuit, a reference detection circuit, acomparator, and a latch circuit. The test detection circuit is coupledbetween a test node and a test line, which corresponds to a first driveline coupled to a memory cell array of a nonvolatile memory device. Thetest detection circuit provides a supply voltage to the test node tocharge the test line, floats the test node and the test line, anddecreases a voltage of the test node based on a leakage current flowingfrom the test line. The reference detection circuit is coupled between areference node and a reference line, which corresponds to a second driveline that is coupled to the memory cell array of the nonvolatile memorydevice and delivers a same type of a drive signal as the first driveline. The reference detection circuit provides the supply voltage to thereference node to charge the reference line, floats the reference nodeand the reference line, and decreases a voltage of the reference nodebased on a self-discharge of the reference line. The comparator outputsa comparison signal by comparing the voltage of the test node with thevoltage of the reference node. The latch circuit latches the comparisonsignal in response to a latch control signal, and outputs the latchedcomparison signal as a test result signal.

In example embodiments, the test detection circuit may include a firstcharge transistor, which is coupled between the supply voltage and thetest node, and includes a gate on which a charge control signal isapplied, a first enable transistor, which is coupled between the testnode and a ground voltage, and includes a gate on which an enable signalis applied, and a first transmission transistor, which is coupledbetween the test line and the test node, and includes a gate on which atransmission control signal is applied. The reference detection circuitmay include a second charge transistor, which is coupled between thesupply voltage and the reference node, and includes a gate on which thecharge control signal is applied, a second enable transistor, which iscoupled between the reference node and the ground voltage, and includesa gate on which the enable signal is applied, and a second transmissiontransistor, which is coupled between the reference line and thereference node, and includes a gate on which the transmission controlsignal is applied.

The leakage current detection device may further include a controlcircuit. The control circuit may turn off the first enable transistorand the second enable transistor using the enable signal, turn on thefirst charge transistor and the second charge transistor using thecharge control signal, and turn on the first transmission transistor andthe second transmission transistor using the transmission control signalat a first time. The control circuit may turn off the first chargetransistor and the second charge transistor using the charge controlsignal to float the test node and the reference node at a second time.The control circuit may provide the latch control signal to the latchcircuit at a third time. A time duration between the second time and thethird time may correspond to a detection time.

The control circuit may adjust a voltage level of the transmissioncontrol signal in a logic high state based on a type of a drive signalthat the test line and the reference line deliver. The control circuitmay adjust a length of the detection time based on a magnitude of theleakage current of the test line to be detected.

In example embodiments, the comparator may change a logic level of thecomparison signal when the voltage of the test node becomes lower thanthe voltage of the reference node by a predetermined voltage.

In example embodiments, each of the test line and the reference line maycorrespond to a word line coupled to the memory cell array of thenonvolatile memory device. In example embodiments, each of the test lineand the reference line may correspond to a string selection line coupledto the memory cell array of the nonvolatile memory device. In exampleembodiments, each of the test line and the reference line may correspondto a ground selection line coupled to the memory cell array of thenonvolatile memory device.

According to example embodiments, a nonvolatile memory device includes amemory cell array, a line selection circuit, a leakage current detectiondevice, and a controller. The memory cell array includes a plurality ofmemory cell blocks. The line selection circuit is coupled to theplurality of memory cell blocks through a plurality of string selectionlines, a plurality of word lines, and a plurality of ground selectionlines. The line selection circuit couples a test line to one of theplurality of string selection lines, the plurality of word lines, andthe plurality of ground selection lines based on a test line selectionsignal, and couples a reference line to another one of the plurality ofstring selection lines, the plurality of word lines, and the pluralityof ground selection lines based on a reference line selection signal.The leakage current detection device charges the test line and thereference line to a same voltage, floats the test line and the referenceline, and generates a test result signal, which indicates whether aleakage current flows from the test line, based on a change of a voltageof the test line and a change of a voltage of the reference line. Thecontroller generates the test line selection signal and the referenceline selection signal.

In example embodiments, the leakage current detection device may includea test detection circuit, a reference detection circuit, a comparator,and a latch circuit. The test detection circuit may be coupled between atest node and the test line. The test detection circuit may provide asupply voltage to the test node to charge the test line, float the testnode and the test line, and decrease a voltage of the test node based ona leakage current flowing from the test line. The reference detectioncircuit may be coupled between a reference node and the reference line.The reference detection circuit may provide the supply voltage to thereference node to charge the reference line, float the reference nodeand the reference line, and decrease a voltage of the reference nodebased on a self-discharge of the reference line. The comparator mayoutput a comparison signal by comparing the voltage of the test nodewith the voltage of the reference node. The latch circuit may latch thecomparison signal in response to a latch control signal, and output thelatched comparison signal as the test result signal.

The test detection circuit include a first charge transistor, which iscoupled between the supply voltage and the test node, and includes agate on which a charge control signal is applied, a first enabletransistor, which is coupled between the test node and a ground voltage,and includes a gate on which an enable signal is applied, and a firsttransmission transistor, which is coupled between the test line and thetest node, and includes a gate on which a transmission control signal isapplied. The reference detection circuit may include a second chargetransistor, which is coupled between the supply voltage and thereference node, and includes a gate on which the charge control signalis applied, a second enable transistor, which is coupled between thereference node and the ground voltage, and includes a gate on which theenable signal is applied, and a second transmission transistor, which iscoupled between the reference line and the reference node, and includesa gate on which the transmission control signal is applied.

In example embodiments, when the test line is coupled to one of theplurality of word lines, the reference line may be coupled to anotherone of the plurality of word lines. When the test line is coupled to oneof the plurality of string selection lines, the reference line may becoupled to another one of the plurality of string selection lines. Whenthe test line is coupled to one of the plurality of ground selectionlines, the reference line may be coupled to another one of the pluralityof ground selection lines.

In example embodiments, the memory cell array may correspond to athree-dimensional memory array.

BRIEF DESCRIPTION OF THE DRAWINGS

Illustrative, non-limiting example embodiments will be more clearlyunderstood from the following detailed description in conjunction withthe accompanying drawings.

FIG. 1 is a block diagram illustrating a leakage current detectiondevice according to example embodiments.

FIG. 2 is a block diagram illustrating an example of a leakage currentdetection device of FIG. 1.

FIGS. 3 and 4 are timing diagrams for describing an operation of theleakage current detection device of FIG. 2.

FIG. 5 is a block diagram illustrating a nonvolatile memory deviceaccording to example embodiments.

FIGS. 6A and 6B are circuit diagrams illustrating examples of a memoryblock included in the nonvolatile memory device of FIG. 5.

FIG. 7 is a block diagram illustrating an example of a nonvolatilememory device of FIG. 5.

FIG. 8 is a block diagram illustrating an example of a nonvolatilememory device of FIG. 5.

FIG. 9 is a block diagram illustrating a nonvolatile memory deviceaccording to example embodiments.

FIG. 10 is a flow chart illustrating a method of detecting a leakagecurrent in a nonvolatile memory device according to example embodiments.

FIG. 11 is a block diagram illustrating a memory system according toexample embodiments.

FIG. 12 is a block diagram illustrating a memory card according toexample embodiments.

FIG. 13 is a block diagram illustrating a solid state drive (SSD) systemaccording to example embodiments.

FIG. 14 is a block diagram illustrating a mobile system according toexample embodiments.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various example embodiments will be described more fully with referenceto the accompanying drawings, in which some example embodiments areshown. The present inventive concept may, however, be embodied in manydifferent forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the present inventive concept to those skilled inthe art. Like reference numerals refer to like elements throughout thisapplication.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the present inventiveconcept. As used herein, the term “and/or” includes any and allcombinations of one or more of the associated listed items.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Other words used to describe therelationship between elements should be interpreted in a like fashion(e.g., “between” versus “directly between,” “adjacent” versus “directlyadjacent,” etc.).

The terminology used herein is for the purpose of describing particularembodiments and is not intended to be limiting of the inventive concept.As used herein, the singular forms “a,” “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises,”“comprising,” “includes” and/or “including,” when used herein, specifythe presence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this inventive concept belongs. Itwill be further understood that terms, such as those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

FIG. 1 is a block diagram illustrating a leakage current detectiondevice according to example embodiments. Referring to FIG. 1, a leakagecurrent detection device 10 includes a test detection circuit 100, areference detection circuit 200, a comparator 300, and a latch circuit400.

The test detection circuit 100 is coupled between a test node TEST_NDand a test line TEST_LN on which a leakage test operation is performed.The test line TEST_LN corresponds to a first drive line among drivelines coupled to a memory cell array of a nonvolatile memory device. Thetest detection circuit 100 provides a supply voltage VDD to the testnode TEST_ND to charge the test line TEST_LN. After that, the testdetection circuit 100 floats the test node TEST_ND and the test lineTEST_LN. The test detection circuit 100 decreases a voltage of the testnode TEST_ND based on a leakage current flowing from the test lineTEST_LN.

The reference detection circuit 200 is coupled between a reference nodeREF_ND and a reference line REF_LN. The reference line REF_LNcorresponds to a second drive line, which is different from the firstdrive line, among the drive lines coupled to the memory cell array ofthe nonvolatile memory device. The first drive line and the second driveline may deliver a same type of a drive signal to the memory cell array.The second drive line may not have a defect such that a substantialleakage current may not flow from the second drive line. The referencedetection circuit 200 provides the supply voltage VDD to the referencenode REF_ND to charge the reference line REF_LN. After that, thereference detection circuit 200 floats the reference node REF_ND and thereference line REF_LN. Since a leakage current does not flow from thereference line REF_LN, the reference detection circuit 200 decreases avoltage of the reference node REF_ND based on a self-discharge of thereference line REF_LN. When a magnitude of the self-discharge of thereference line REF_LN is negligibly small, the voltage of the referencenode REF_ND may be maintained without a substantial change after thereference node REF_ND and the reference line REF_LN are floated.

In some example embodiments, each of the test line TEST_LN and thereference line REF_LN may correspond to a word line delivering a wordline signal to the memory cell array of the nonvolatile memory device.In some example embodiments, each of the test line TEST_LN and thereference line REF_LN may correspond to a string selection linedelivering a string selection signal to the memory cell array of thenonvolatile memory device. In some example embodiments, each of the testline TEST_LN and the reference line REF_LN may correspond to a groundselection line delivering a ground selection signal to the memory cellarray of the nonvolatile memory device.

The comparator 300 outputs a comparison signal CMP by comparing thevoltage of the test node TEST_ND with the voltage of the reference nodeREF_ND. In some example embodiments, the comparator 300 may change alogic level of the comparison signal CMP when the voltage of the testnode TEST_ND becomes lower than the voltage of the reference node REF_NDby a predetermined voltage. For example, the comparator 300 may outputthe comparison signal CMP having a logic low level when the voltage ofthe test node TEST_ND is equal to or higher than a voltage, which islower than the voltage of the reference node REF_ND by the predeterminedvoltage. Alternately, the comparator 300 may output the comparisonsignal CMP having a logic high level when the voltage of the test nodeTEST_ND is lower than the voltage, which is lower than the voltage ofthe reference node REF_ND by the predetermined voltage. The latchcircuit 400 latches the comparison signal CMP in response to a latchcontrol signal LCS, and output the latched comparison signal as a testresult signal TEST_RE, which indicates whether a leakage current flowsfrom the test line TEST_LN.

FIG. 2 is a block diagram illustrating an example of a leakage currentdetection device of FIG. 1. Referring to FIG. 2, a leakage currentdetection device 10 a may include a test detection circuit 100 a, areference detection circuit 200 a, a comparator 300, and a latch circuit400. The comparator 300 and the latch circuit 400 included in theleakage current detection device 10 a of FIG. 2 may be the same as thecomparator 300 and the latch circuit 400 included in the leakage currentdetection device 10 of FIG. 1.

The test detection circuit 100 a may include a first charge transistor110, a first transmission transistor 120, and a first enable transistor130. The first charge transistor 110 may be coupled between the supplyvoltage VDD and the test node TEST_ND, and include a gate on which acharge control signal CCS is applied. The first transmission transistor120 may be coupled between the test line TEST_LN and the test nodeTEST_ND, and include a gate on which a transmission control signal TCSis applied. The first enable transistor 130 may be coupled between thetest node TEST_ND and a ground voltage GND, and include a gate on whichan enable signal EN is applied.

The reference detection circuit 200 a may include a second chargetransistor 210, a second transmission transistor 220, and a secondenable transistor 230. The second charge transistor 210 may be coupledbetween the supply voltage VDD and the reference node REF_ND, andinclude a gate on which the charge control signal CCS is applied. Thesecond transmission transistor 220 may be coupled between the referenceline REF_LN and the reference node REF_ND, and include a gate on whichthe transmission control signal TCS is applied. The second enabletransistor 230 may be coupled between the reference node REF_ND and theground voltage GND, and include a gate on which the enable signal EN isapplied.

In some example embodiments, each of the first charge transistor 110 andthe second charge transistor 210 may include a p-type metal oxidesemiconductor (PMOS) transistor, and each of the first transmissiontransistor 120, the second transmission transistor 220, the first enabletransistor 130, and the second enable transistor 230 may include ann-type metal oxide semiconductor (NMOS) transistor.

In some example embodiments, the leakage current detection device 10 amay further include a control circuit 450 that provides the chargecontrol signal CCS to the first charge transistor 110 and the secondcharge transistor 210, provides the transmission control signal TCS tothe first transmission transistor 120 and the second transmissiontransistor 220, provides the enable signal EN to the first enabletransistor 130 and the second enable transistor 230, and provides thelatch control signal LCS to the latch circuit 400.

FIGS. 3 and 4 are timing diagrams for describing an operation of theleakage current detection device of FIG. 2. FIG. 3 illustrates anoperation of the leakage current detection device 10 a of FIG. 2 when aleakage current does not flow from the test line TEST_LN. FIG. 4illustrates an operation of the leakage current detection device 10 a ofFIG. 2 when a leakage current flows from the test line TEST_LN.

Hereinafter, an operation of the leakage current detection device 10 aof FIG. 2 in the case that a leakage current does not flow from the testline TEST_LN is described with reference to FIGS. 2 and 3. Referring toFIGS. 2 and 3, at a first time T1, the control circuit 450 may providethe enable signal EN having the logic low level to the first enabletransistor 130 and the second enable transistor 230 to turn off thefirst enable transistor 130 and the second enable transistor 230,provide the charge control signal CCS having the logic low level to thefirst charge transistor 110 and the second charge transistor 210 to turnon the first charge transistor 110 and the second charge transistor 210,and provide the transmission control signal TCS having the logic highlevel to the first transmission transistor 120 and the secondtransmission transistor 220 to turn on the first transmission transistor120 and the second transmission transistor 220.

Therefore, the voltage V_TEST_ND of the test node TEST_ND and thevoltage V_REF_ND of the reference node REF_ND may increase to the supplyvoltage VDD. In addition, the test line TEST_LN and the reference lineREF_LN may be charged with charges received from the test node TEST_NDand the reference node REF_ND, respectively, such that the voltageV_TEST_LN of the test line TEST_LN and the voltage V_REF_LN of thereference line REF_LN may also increase. For example, as illustrated inFIG. 3, the test line TEST_LN may be charged up to a voltage that islower than a voltage of the transmission control signal TCS, which isapplied on the gate of the first transmission transistor 120, by athreshold voltage Vth of the first transmission transistor 120.Similarly, the reference line REF_LN may be charged up to a voltage thatis lower than a voltage of the transmission control signal TCS, which isapplied on the gate of the second transmission transistor 220, by athreshold voltage Vth of the second transmission transistor 220. Thethreshold voltage Vth of the first transmission transistor 120 may bethe same as the threshold voltage Vth of the second transmissiontransistor 220.

In some example embodiments, the control circuit 450 may adjust avoltage level of the transmission control signal TCS in a logic highstate. For example, as illustrated in FIG. 3, the control circuit 450may adjust the voltage level of the transmission control signal TCS inthe logic high state between a first voltage V1 and a second voltage V2based on a type of a drive signal that the test line TEST_LN and thereference line REF_LN deliver.

For example, when each of the test line TEST_LN and the reference lineREF_LN corresponds to a word line of the nonvolatile memory device thatdelivers a signal having a relatively high voltage, the control circuit450 may increase the voltage level of the transmission control signalTCS in the logic high state. When each of the test line TEST_LN and thereference line REF_LN corresponds to a string selection line or a groundselection line of the nonvolatile memory device that delivers a signalhaving a relatively low voltage, the control circuit 450 may decreasethe voltage level of the transmission control signal TCS in the logichigh state. Therefore, the control circuit 450 may control a chargelevel of the test line TEST_LN and the reference line REF_LN byadjusting the voltage level of the transmission control signal TCS inthe logic high state.

At a second time T2, the control circuit 450 may provide the chargecontrol signal CCS having the logic high level to the first chargetransistor 110 and the second charge transistor 210 to turn off thefirst charge transistor 110 and the second charge transistor 210. Sincethe test node TEST_ND and the reference node REF_ND are disconnectedfrom the supply voltage VDD and the ground voltage GND, the test nodeTEST_ND and the reference node REF_ND may be floated. Since the testnode TEST_ND and the reference node REF_ND are floated, the test lineTEST_LN and the reference line REF_LN may also be floated.

When a leakage current does not flow from the test line TEST_LN, thevoltage V_TEST_LN of the test line TEST_LN and the voltage V_TEST_ND ofthe test node TEST_ND may decrease based on a self-discharge of the testline TEST_LN. Similarly, the voltage V_REF_LN of the reference lineREF_LN and the voltage V_REF_ND of the reference node REF_ND maydecrease based on the self-discharge of the reference line REF_LN.

As described above, since the test line TEST_LN and the reference lineREF_LN deliver a same type of a drive signal to the memory cell array, amagnitude of the self-discharge of the test line TEST_LN may besubstantially the same as a magnitude of the self-discharge of thereference line REF_LN. Therefore, a decrease amount of the voltageV_TEST_ND of the test node TEST_ND may be substantially the same as adecrease amount of the voltage V_REF_ND of the reference node REF_NDafter the second time T2.

When the magnitude of the self-discharge of the test line TEST_LN andthe reference line REF_LN is negligibly small, as illustrated in FIG. 3,the voltage V_TEST_LN of the test line TEST_LN, the voltage V_TEST_ND ofthe test node TEST_ND, the voltage V_REF_LN of the reference lineREF_LN, and the voltage V_REF_ND of the reference node REF_ND may bemaintained without a substantial change after the second time T2.

At a third time T3, the control circuit 450 may provide the transmissioncontrol signal TCS having the logic low level to the first transmissiontransistor 120 and the second transmission transistor 220 to turn offthe first transmission transistor 120 and the second transmissiontransistor 220. Therefore, the voltage V_TEST_ND of the test nodeTEST_ND and the voltage V_REF_ND of the reference node REF_ND may bemaintained without a substantial change after the third time T3. Inaddition, the control circuit 450 may provide the latch control signalLCS having the logic high level to the latch circuit 400 at the thirdtime T3. Therefore, the latch circuit 400 may latch the comparisonsignal CMP output from the comparator 300 at the third time T3, andoutput the latched comparison signal as the test result signal TEST_RE.The time duration between the second time T2 and the third time T3 maybe referred to as a detection time Td.

As illustrated in FIG. 3, when a leakage current does not flow from thetest line TEST_LN, the voltage V_TEST_ND of the test node TEST_ND may bethe same as the voltage V_REF_ND of the reference node REF_ND at thethird time T3. Therefore, the comparator 300 may output the comparisonsignal CMP having the logic low level, and the latch circuit 400 mayoutput the test result signal TEST_RE having the logic low level.

At a fourth time T4, the control circuit 450 may provide the enablesignal EN having the logic high level to the first enable transistor 130and the second enable transistor 230 to turn on the first enabletransistor 130 and the second enable transistor 230. Therefore, thevoltage V_TEST_ND of the test node TEST_ND and the voltage V_REF_ND ofthe reference node REF_ND may be reset to the ground voltage GND and bemaintained at the ground voltage GND. The leakage test operation on thetest line TEST_LN may be finished at the fourth time T4.

Hereinafter, an operation of the leakage current detection device 10 aof FIG. 2 in the case that a leakage current flows from the test lineTEST_LN is described with reference to FIGS. 2 and 4. Referring to FIGS.2 and 4, at a first time T1, the control circuit 450 may provide theenable signal EN having the logic low level to the first enabletransistor 130 and the second enable transistor 230 to turn off thefirst enable transistor 130 and the second enable transistor 230,provide the charge control signal CCS having the logic low level to thefirst charge transistor 110 and the second charge transistor 210 to turnon the first charge transistor 110 and the second charge transistor 210,and provide the transmission control signal TCS having the logic highlevel to the first transmission transistor 120 and the secondtransmission transistor 220 to turn on the first transmission transistor120 and the second transmission transistor 220.

Therefore, the voltage V_TEST_ND of the test node TEST_ND and thevoltage V_REF_ND of the reference node REF_ND may increase to the supplyvoltage VDD. In addition, the test line TEST_LN and the reference lineREF_LN may be charged with charges received from the test node TEST_NDand the reference node REF_ND, respectively, such that the voltageV_TEST_LN of the test line TEST_LN and the voltage V_REF_LN of thereference line REF_LN may also increase. For example, as illustrated inFIG. 4, the test line TEST_LN may be charged up to a voltage that islower than a voltage of the transmission control signal TCS, which isapplied on the gate of the first transmission transistor 120, by athreshold voltage Vth of the first transmission transistor 120.Similarly, the reference line REF_LN may be charged up to a voltage thatis lower than a voltage of the transmission control signal TCS, which isapplied on the gate of the second transmission transistor 220, by athreshold voltage Vth of the second transmission transistor 220. Thethreshold voltage Vth of the first transmission transistor 120 may bethe same as the threshold voltage Vth of the second transmissiontransistor 220.

In some example embodiments, the control circuit 450 may adjust avoltage level of the transmission control signal TCS in a logic highstate. For example, as illustrated in FIG. 4, the control circuit 450may adjust the voltage level of the transmission control signal TCS inthe logic high state between a first voltage V1 and a second voltage V2based on a type of a drive signal that the test line TEST_LN and thereference line REF_LN deliver.

For example, when each of the test line TEST_LN and the reference lineREF_LN corresponds to a word line of the nonvolatile memory device thatdelivers a signal having a relatively high voltage, the control circuit450 may increase the voltage level of the transmission control signalTCS in the logic high state. When each of the test line TEST_LN and thereference line REF_LN corresponds to a string selection line or a groundselection line of the nonvolatile memory device that delivers a signalhaving a relatively low voltage, the control circuit 450 may decreasethe voltage level of the transmission control signal TCS in the logichigh state. Therefore, the control circuit 450 may control a chargelevel of the test line TEST_LN and the reference line REF_LN byadjusting the voltage level of the transmission control signal TCS inthe logic high state.

At a second time T2, the control circuit 450 may provide the chargecontrol signal CCS having the logic high level to the first chargetransistor 110 and the second charge transistor 210 to turn off thefirst charge transistor 110 and the second charge transistor 210. Sincethe test node TEST_ND and the reference node REF_ND are disconnectedfrom the supply voltage VDD and the ground voltage GND, the test nodeTEST_ND and the reference node REF_ND may be floated. Since the testnode TEST_ND and the reference node REF_ND are floated, the test lineTEST_LN and the reference line REF_LN may also be floated.

Therefore, the voltage V_REF_LN of the reference line REF_LN and thevoltage V_REF_ND of the reference node REF_ND may decrease based on theself-discharge of the reference line REF_LN. When the magnitude of theself-discharge of the reference line REF_LN is negligibly small, asillustrated in FIG. 4, the voltage V_REF_LN of the reference line REF_LNand the voltage V_REF_ND of the reference node REF_ND may be maintainedwithout a substantial change after the second time T2.

When the test line TEST_LN has a defect such that a leakage current,which has a magnitude substantially greater than the magnitude of theself-discharge, flows from the test line TEST_LN, as illustrated in FIG.4, the voltage V_TEST_LN of the test line TEST_LN and the voltageV_TEST_ND of the test node TEST_ND may decrease based on the leakagecurrent flowing from the test line TEST_LN, such that the voltageV_TEST_LN of the test line TEST_LN and the voltage V_TEST_ND of the testnode TEST_ND may become lower than the voltage V_REF_LN of the referenceline REF_LN and the voltage V_REF_ND of the reference node REF_ND,respectively.

At a third time T3, the control circuit 450 may provide the transmissioncontrol signal TCS having the logic low level to the first transmissiontransistor 120 and the second transmission transistor 220 to turn offthe first transmission transistor 120 and the second transmissiontransistor 220. Therefore, the voltage V_TEST_ND of the test nodeTEST_ND and the voltage V_REF_ND of the reference node REF_ND may bemaintained without a substantial change after the third time T3. Inaddition, the control circuit 450 may provide the latch control signalLCS having the logic high level to the latch circuit 400 at the thirdtime T3. Therefore, the latch circuit 400 may latch the comparisonsignal CMP output from the comparator 300 at the third time T3, andoutput the latched comparison signal as the test result signal TEST_RE.The time duration between the second time T2 and the third time T3 maybe referred to as the detection time Td.

As illustrated in FIG. 4, when the leakage current flows from the testline TEST_LN, the voltage V_TEST_ND of the test node TEST_ND may belower than the voltage V_REF_ND of the reference node REF_ND at thethird time T3. The comparator 300 may output the comparison signal CMPhaving the logic low level when the voltage V_TEST_ND of the test nodeTEST_ND is equal to or higher than a voltage, which is lower than thevoltage V_REF_ND of the reference node REF_ND by the predeterminedvoltage. Alternately, the comparator 300 may output the comparisonsignal CMP having the logic high level when the voltage V_TEST_ND of thetest node TEST_ND is lower than the voltage, which is lower than thevoltage V_REF_ND of the reference node REF_ND by the predeterminedvoltage. The latch circuit 400 may latch the comparison signal CMPoutput from the comparator 300 at the third time T3, and output thelatched comparison signal as the test result signal TEST_RE.

The greater the magnitude of the leakage current flowing from the testline TEST_LN, the greater a decrease rate of the voltage V_TEST_ND ofthe test node TEST_ND during the detection time Td. Alternately, thesmaller the magnitude of the leakage current flowing from the test lineTEST_LN, the smaller the decrease rate of the voltage V_TEST_ND of thetest node TEST_ND during the detection time Td.

In some example embodiments, the control circuit 450 may adjust a lengthof the detection time Td based on a minimum magnitude of the leakagecurrent to be detected. The greater the length of the detection time Td,the smaller the minimum magnitude of the leakage current that theleakage current detection device 10 a is able to detect.

At a fourth time T4, the control circuit 450 may provide the enablesignal EN having the logic high level to the first enable transistor 130and the second enable transistor 230 to turn on the first enabletransistor 130 and the second enable transistor 230. Therefore, thevoltage V_TEST_ND of the test node TEST_ND and the voltage V_REF_ND ofthe reference node REF_ND may be reset to the ground voltage GND and bemaintained at the ground voltage GND. The leakage test operation on thetest line TEST_LN may be finished at the fourth time T4. Generally,magnitudes of self-discharge of drive lines that deliver a same type ofa drive signal to a memory cell array of a nonvolatile memory device maybe the same.

As described above with reference to FIGS. 1 to 4, the leakage currentdetection device 10 may select the test line TEST_LN and the referenceline REF_LN that deliver a same type of a drive signal among drive linescoupled to a memory cell array of a nonvolatile memory device. Thereference line REF_LN may not have a defect such that a substantialleakage current may not flow from the reference line REF_LN. The leakagecurrent detection device 10 may charge the test line TEST_LN and thereference line REF_LN to the same voltage level. After that, the leakagecurrent detection device 10 may generate the test result signal TEST_RE,which indicates whether a leakage current flows from the test lineTEST_LN, by comparing a decrease amount of the voltage V_TEST_ND of thetest node TEST_ND, which may be caused by a leakage current flowing fromthe test line TEST_LN or a self-discharge of the test line TEST_LN, witha decrease in amount of the voltage V_REF_ND of the reference nodeREF_ND, which may be caused by a self-discharge of the reference lineREF_LN.

Therefore, the leakage current detection device 10 according to exampleembodiments may effectively detect a leakage current flowing from adrive line coupled to the memory cell array of the nonvolatile memorydevice.

FIG. 5 is a block diagram illustrating a nonvolatile memory deviceaccording to example embodiments. Referring to FIG. 5, a nonvolatilememory device 20 includes a memory cell array 500, a line selectioncircuit 600, a controller 700, a data input/output (I/O) circuit 800,and a leakage current detection device 10.

The memory cell array 500 may include a plurality of memory blocks510-1, 510-2, . . . , 510-m. The plurality of memory blocks 510-1,510-2, . . . , 510-m may be coupled to the line selection circuit 600through a plurality of drive lines. For example, the plurality of memoryblocks 510-1, 510-2, . . . , 510-m may be coupled to the line selectioncircuit 600 through a plurality of string selection lines SSL1, SSL2, .. . , SSLm, a plurality of word lines WL11˜WL1 n, WL21˜WL2 n, . . . ,WLm1˜WLmn, a plurality of ground selection lines GSL1, GSL2, . . . ,GSLm, and a plurality of common source lines CSL1, CSL2, . . . , CSLm.In addition, the plurality of memory blocks 510-1, 510-2, . . . , 510-mmay be coupled to the data I/O circuit 800 through a plurality of bitlines BL1, BL2, . . . , BLz. Here, n, m, and z represent positiveintegers. Each of the plurality of memory blocks 510-1, 510-2, . . . ,510-m may include a plurality of memory cell strings 520.

FIGS. 6A and 6B are circuit diagrams illustrating examples of a memoryblock included in the nonvolatile memory device of FIG. 5. A memoryblock 510-1 a of FIG. 6A may be formed on a substrate in athree-dimensional structure (or vertical structure). For example, theplurality of memory cell strings 520 included in the memory block 510-1a may be formed perpendicular to the substrate.

Referring to FIG. 6A, the memory block 510-1 a may include memory cellstrings NS11 to NS33 coupled between bit lines BL1, BL2, and BL3 and acommon source line CSL1. Each of the memory cell strings NS11 to NS33may include a string selection transistor SST, a plurality of memorycells MC1, MC1, . . . , MC8, and a ground selection transistor GST.

In FIG. 6A, each of the memory cell strings NS11 to NS33 is illustratedto include eight memory cells MC1, MC1, . . . , MC8. However, exampleembodiments are not limited thereto. In some example embodiments, eachof the memory cell strings NS11 to NS33 may include any number of memorycells.

The string selection transistor SST may be connected to correspondingstring selection lines SSL11, SSL12, and SSL13. The plurality of memorycells MC1, MC2, . . . , MC8 may be connected to corresponding word linesWL11, WL12, . . . , WL18, respectively. The ground selection transistorGST may be connected to corresponding ground selection lines GSL11,GSL12, and GSL13. The string selection transistor SST may be connectedto corresponding bit lines BL1, BL2 and BL3, and the ground selectiontransistor GST may be connected to the common source line CSL1. Wordlines (e.g., WL1) having the same height may be commonly connected, andthe ground selection lines GSL11, GSL12, and GSL13 and the stringselection lines SSL11, SSL12, and SSL13 may be separated.

As described above with reference to FIG. 6A, the memory cell array 500may be a three dimensional (3D) memory array. The 3D memory array ismonolithically formed in one or more physical levels of arrays of memorycells having an active area disposed above a silicon substrate andcircuitry associated with the operation of those memory cells, whethersuch associated circuitry is above or within such substrate. The term“monolithic” means that layers of each level of the array are directlydeposited on the layers of each underlying level of the array. In anembodiment of the present inventive concept, the 3D memory arrayincludes vertical NAND strings that are vertically oriented such that atleast one memory cell is located over another memory cell. The at leastone memory cell may comprise a charge trap layer. The following patentdocuments, which are hereby incorporated by reference, describe suitableconfigurations for three-dimensional memory arrays, in which thethree-dimensional memory array is configured as a plurality of levels,with word lines and/or bit lines shared between levels: U.S. Pat. Nos.7,679,133; 8,553,466; 8,654,587; 8,559,235; and US Pat. Pub. No.2011/0233648.

A memory block 510-1 b of FIG. 6B may be formed on a substrate in atwo-dimensional structure (or horizontal structure). For example, theplurality of memory cell strings 520 included in the memory block 510-1b may be formed parallel to the substrate. Referring to FIG. 6B, thememory block 510-1 b may include memory cell strings NS1, NS2, NS3, . .. , NSz. Each of the memory cell strings NS1, NS2, NS3, . . . , NSz mayinclude a string selection transistor SST, a plurality of memory cellsMC, and a ground selection transistor GST that are serially connected toeach other.

The string selection transistor SST included in each of the memory cellstrings NS1, NS2, NS3, . . . , NSz may be commonly connected to thestring selection line SSL1. Memory cells arranged in the same row in thememory cell strings NS1, NS2, NS3, . . . , NSz may be commonly connectedto corresponding word lines WL11, WL12, WL13, WL14, . . . , WL1(n−1),WL1 n. The ground selection transistor GST included in each of thememory cell strings NS1, NS2, NS3, . . . , NSz may be commonly connectedto the ground selection line GSL1.

The ground selection transistors GST included in the memory cell stringsNS1, NS2, NS3, . . . , NSz may be commonly connected to the commonsource line CSL1. The string selection transistor SST included in eachof the memory cell strings NS1, NS2, NS3, . . . , NSz may be connectedto corresponding bit lines BL1, BL2, BL3, . . . , BLz. Each of theplurality of memory blocks 510-1, 510-2, . . . , 510-m included in thememory cell array 500 of FIG. 5 may be implemented with the memory block510-1 a of FIG. 6A or the memory block 510-1 b of FIG. 6B.

As described above with reference to FIGS. 5, 6A, and 6B, since each ofthe plurality of memory cell strings 520 included in the plurality ofmemory blocks 510-1, 510-2, . . . , 510-m may have a same structure inwhich the string selection transistor SST, the memory cells MC, and theground selection transistors GST are arranged in the same way, parasiticcapacitances of drive lines of a same type may be substantially thesame. Therefore, magnitudes of a self-discharge of drive lines of a sametype may be substantially the same. For example, magnitudes ofself-discharge of the plurality of string selection lines SSL1, SSL2, .. . , SSLm may be substantially the same, magnitudes of self-dischargeof the plurality of word lines WL11˜WL1 n, WL21˜WL2 n, . . . , WLm1˜WLmnmay be substantially the same, and magnitudes of self-discharge of theplurality of ground selection lines GSL1, GSL2, . . . , GSLm may besubstantially the same.

Referring again to FIG. 5, the data I/O circuit 800 may be coupled tothe memory cell array 500 through the plurality of bit lines BL1, BL2, .. . , BLz. The data I/O circuit 800 may output data DATA read from thememory cells MC through the plurality of bit lines BL1, BL2, . . . , BLzto an external device, and write data DATA received from the externaldevice in the memory cells MC through the plurality of bit lines BL1,BL2, . . . , BLz. In some example embodiments, the data I/O circuit 800may include a sense amplifier, a page buffer, a column selectioncircuit, a write driver, a data buffer, etc.

The line selection circuit 600 may be coupled to the plurality of memoryblocks 510-1, 510-2, . . . , 510-m included in the memory cell array 500through the plurality of string selection lines SSL1, SSL2, . . . ,SSLm, the plurality of word lines WL11˜WL1 n, WL21˜WL2 n, . . . ,WLm1˜WLmn, the plurality of ground selection lines GSL1, GSL2, . . . ,GSLm, and the plurality of common source lines CSL1, GSL2, . . . , CSLm.

The line selection circuit 600 may receive a test line selection signalTLSS and a reference line selection signal RLSS from the controller 700.The line selection circuit 600 may couple a test line TEST_LN to one ofthe plurality of string selection lines SSL1, SSL2, . . . , SSLm, theplurality of word lines WL11˜WL1 n, WL21˜WL2 n, . . . , WLm1˜WLmn, andthe plurality of ground selection lines GSL1, GSL2, . . . , GSLm basedon the test line selection signal TLSS. The line selection circuit 600may couple a reference line REF_LN to another one of the plurality ofstring selection lines SSL1, SSL2, . . . , SSLm, the plurality of wordlines WL11˜WL1 n, WL21˜WL2 n, . . . , WLm1˜WLmn, and the plurality ofground selection lines GSL1, GSL2, . . . , GSLm based on the referenceline selection signal RLSS.

In some example embodiments, when the test line TEST_LN is coupled toone of the plurality of word lines WL11˜WL1 n, WL21˜WL2 n, . . . ,WLm1˜WLmn, the reference line REF_LN may be coupled to another one ofthe plurality of word lines WL11˜WL1 n, WL21˜WL2 n, . . . , WLm1˜WLmn.When the test line TEST_LN is coupled to one of the plurality of stringselection lines SSL1, SSL2, . . . , SSLm, the reference line REF_LN maybe coupled to another one of the plurality of string selection linesSSL1, SSL2, . . . , SSLm. When the test line TEST_LN is coupled to oneof the plurality of ground selection lines GSL1, GSL2, . . . , GSLm, thereference line REF_LN may be coupled to another one of the plurality ofground selection lines GSL1, GSL2, . . . , GSLm.

In some example embodiments, the test line TEST_LN and the referenceline REF_LN may be coupled to drive lines connected to a same memoryblock. In other example embodiments, the test line TEST_LN and thereference line REF_LN may be coupled to drive lines connected todifferent memory blocks.

In some example embodiments, the controller 700 may receive a leakagetest command LTC and a leakage test address LTA from outside. Thecontroller 700 may generate control signals CONS based on the leakagetest command LTC, and generate the test line selection signal TLSS andthe reference line selection signal RLSS based on the leakage testaddress LTA.

In some example embodiments, the controller 700 may include a normalline table NLT 710, which stores addresses of normal lines, from which asubstantial leakage current does not flow, among the plurality of stringselection lines SSL1, SSL2, . . . , SSLm, the plurality of word linesWL11˜WL1 n, WL21˜WL2 n, . . . , WLm1˜WLmn, and the plurality of groundselection lines GSL1, GSL2, . . . , GSLm. In this case, the referenceline selection signal RLSS generated by the controller 700 maycorrespond to one of the addresses of the normal lines stored in thenormal line table 710.

For example, the controller 700 may generate the test line selectionsignal TLSS indicating one of the plurality of string selection linesSSL1, SSL2, . . . , SSLm, the plurality of word lines WL11˜WL1 n,WL21˜WL2 n, . . . , WLm1˜WLmn, and the plurality of ground selectionlines GSL1, GSL2, . . . , GSLm that is represented by the leakage testaddress LTA. In addition, when the leakage test address LTA representsone of the plurality of string selection lines SSL1, SSL2, . . . , SSLm,the controller 700 may generate the reference line selection signal RLSScorresponding to an address of a string selection line among theaddresses of the normal lines stored in the normal line table 710. Whenthe leakage test address LTA represents one of the plurality of wordlines WL11˜WL1 n, WL21˜WL2 n, . . . , WLm1˜WLmn, the controller 700 maygenerate the reference line selection signal RLSS corresponding to anaddress of a word line among the addresses of the normal lines stored inthe normal line table 710. When the leakage test address LTA representsone of the plurality of ground selection lines GSL1, GSL2, . . . , GSLm,the controller 700 may generate the reference line selection signal RLSScorresponding to an address of a ground selection line among theaddresses of the normal lines stored in the normal line table 710.

The leakage current detection device 10 may operate based on the controlsignals CONS provided by the controller 700. The leakage currentdetection device 10 may charge the test line TEST_LN and the referenceline REF_LN to a same voltage, float the test line TEST_LN and thereference line REF_LN, and generate a test result signal TEST_RE, whichindicates whether a leakage current flows from the test line TEST_LN,based on a change of a voltage of the test line TEST_LN and a change ofa voltage of the reference line REF_LN.

FIG. 7 is a block diagram illustrating an example of a nonvolatilememory device of FIG. 5. Referring to FIG. 7, a nonvolatile memorydevice 20 a may include a memory cell array 500, a line selectioncircuit 600, a controller 700, a data I/O circuit 800, and a leakagecurrent detection device 10. The memory cell array 500, the lineselection circuit 600, the controller 700, and the data I/O circuit 800included in the nonvolatile memory device 20 a of FIG. 7 may be the sameas the memory cell array 500, the line selection circuit 600, thecontroller 700, and the data I/O circuit 800 included in the nonvolatilememory device 20 of FIG. 5.

The leakage current detection device 10 included in the nonvolatilememory device 20 a may include a test detection circuit 100, a referencedetection circuit 200, a comparator 300, and a latch circuit 400. Thetest detection circuit 100 may be coupled between a test node TEST_NDand the test line TEST_LN. As described above, the test line TEST_LN maybe coupled to one of the plurality of string selection lines SSL1, SSL2,. . . , SSLm, the plurality of word lines WL11˜WL1 n, WL21˜WL2 n, . . ., WLm1˜WLmn, and the plurality of ground selection lines GSL1, GSL2, . .. , GSLm.

The test detection circuit 100 may provide a supply voltage VDD to thetest node TEST_ND to charge the test line TEST_LN. After that, the testdetection circuit 100 may float the test node TEST_ND and the test lineTEST_LN. The test detection circuit 100 may decrease a voltage of thetest node TEST_ND based on a leakage current flowing from the test lineTEST_LN.

The reference detection circuit 200 may be coupled between a referencenode REF_ND and the reference line REF_LN. As described above, when thetest line TEST_LN is coupled to one of the plurality of word linesWL11˜WL1 n, WL21˜WL2 n, . . . , WLm1˜WLmn, the reference line REF_LN maybe coupled to another one of the plurality of word lines WL11˜WL1 n,WL21˜WL2 n, . . . , WLm1˜WLmn from which a substantial leakage currentdoes not flow. When the test line TEST_LN is coupled to one of theplurality of string selection lines SSL1, SSL2, . . . , SSLm, thereference line REF_LN may be coupled to another one of the plurality ofstring selection lines SSL1, SSL2, . . . , SSLm from which a substantialleakage current does not flow. When the test line TEST_LN is coupled toone of the plurality of ground selection lines GSL1, GSL2, . . . , GSLm,the reference line REF_LN may be coupled to another one of the pluralityof ground selection lines GSL1, GSL2, . . . , GSLm from which asubstantial leakage current does not flow.

The reference detection circuit 200 may provide the supply voltage VDDto the reference node REF_ND to charge the reference line REF_LN. Afterthat, the reference detection circuit 200 may float the reference nodeREF_ND and the reference line REF_LN. Since a leakage current does notflow from the reference line REF_LN, the reference detection circuit 200may decrease a voltage of the reference node REF_ND based on aself-discharge of the reference line REF_LN. When a magnitude of theself-discharge of the reference line REF_LN is negligibly small, thevoltage of the reference node REF_ND may be maintained without asubstantial change after the reference node REF_ND and the referenceline REF_LN are floated.

The comparator 300 may output a comparison signal CMP by comparing thevoltage of the test node TEST_ND with the voltage of the reference nodeREF_ND. In some example embodiments, the comparator 300 may change alogic level of the comparison signal CMP when the voltage of the testnode TEST_ND becomes lower than the voltage of the reference node REF_NDby a predetermined voltage. For example, the comparator 300 may outputthe comparison signal CMP having a logic low level when the voltage ofthe test node TEST_ND is equal to or higher than a voltage, which islower than the voltage of the reference node REF_ND by the predeterminedvoltage. Alternately, the comparator 300 may output the comparisonsignal CMP having a logic high level when the voltage of the test nodeTEST_ND is lower than the voltage, which is lower than the voltage ofthe reference node REF_ND by the predetermined voltage.

The latch circuit 400 may latch the comparison signal CMP in response toa latch control signal LCS provided by the controller 700, and outputthe latched comparison signal as a test result signal TEST_RE.Therefore, the test result signal TEST_RE may indicate whether a leakagecurrent flows from a drive line coupled to the test line TEST_LN amongthe plurality of string selection lines SSL1, SSL2, . . . , SSLm, theplurality of word lines WL11˜WL1 n, WL21˜WL2 n, . . . , WLm1˜WLmn, andthe plurality of ground selection lines GSL1, GSL2, . . . , GSLm.

FIG. 8 is a block diagram illustrating an example of a nonvolatilememory device of FIG. 5. Referring to FIG. 8, a nonvolatile memorydevice 20 b may include a memory cell array 500, a line selectioncircuit 600, a controller 700, a data I/O circuit 800, and a leakagecurrent detection device 10 b. The memory cell array 500, the lineselection circuit 600, the controller 700, and the data I/O circuit 800included in the nonvolatile memory device 20 b of FIG. 8 may be the sameas the memory cell array 500, the line selection circuit 600, thecontroller 700, and the data I/O circuit 800 included in the nonvolatilememory device 20 of FIG. 5.

The leakage current detection device 10 b included in the nonvolatilememory device 20 b may include a test detection circuit 100 a, areference detection circuit 200 a, a comparator 300, and a latch circuit400. The test detection circuit 100 a may include a first chargetransistor 110, a first transmission transistor 120, and a first enabletransistor 130. The first charge transistor 110 may be coupled betweenthe supply voltage VDD and the test node TEST_ND, and include a gate onwhich a charge control signal CCS is applied. The first transmissiontransistor 120 may be coupled between the test line TEST_LN and the testnode TEST_ND, and include a gate on which a transmission control signalTCS is applied. The first enable transistor 130 may be coupled betweenthe test node TEST_ND and a ground voltage GND, and include a gate onwhich an enable signal EN is applied.

The reference detection circuit 200 a may include a second chargetransistor 210, a second transmission transistor 220, and a secondenable transistor 230. The second charge transistor 210 may be coupledbetween the supply voltage VDD and the reference node REF_ND, andinclude a gate on which the charge control signal CCS is applied. Thesecond transmission transistor 220 may be coupled between the referenceline REF_LN and the reference node REF_ND, and include a gate on whichthe transmission control signal TCS is applied. The second enabletransistor 230 may be coupled between the reference node REF_ND and theground voltage GND, and include a gate on which the enable signal EN isapplied.

In some example embodiments, each of the first charge transistor 110 andthe second charge transistor 210 may include a p-type metal oxidesemiconductor (PMOS) transistor, and each of the first transmissiontransistor 120, the second transmission transistor 220, the first enabletransistor 130, and the second enable transistor 230 may include ann-type metal oxide semiconductor (NMOS) transistor.

The controller 700 may provide the charge control signal CCS to thefirst charge transistor 110 and the second charge transistor 210,provide the transmission control signal TCS to the first transmissiontransistor 120 and the second transmission transistor 220, provide theenable signal EN to the first enable transistor 130 and the secondenable transistor 230, and provide the latch control signal LCS to thelatch circuit 400 based on the leakage test command LTC.

The test detection circuit 100 a, the reference detection circuit 200 a,the comparator 300, and the latch circuit 400 included in the leakagecurrent detection device 10 b of FIG. 8 may be the same as the testdetection circuit 100 a, the reference detection circuit 200 a, thecomparator 300, and the latch circuit 400 included in the leakagecurrent detection device 10 a of FIG. 2. In addition, the controller 700included in the nonvolatile memory device 20 b of FIG. 8 may perform theoperation of the control circuit 450 included in the leakage currentdetection device 10 a of FIG. 2.

As described above with reference to FIGS. 1 to 8, the nonvolatilememory device 20 including the leakage current detection device 10 maycouple the test line TEST_LN and the reference line REF_LN to drivelines of a same type among the plurality of string selection lines SSL1,SSL2, . . . , SSLm, the plurality of word lines WL11˜WL1 n, WL21˜WL2 n,. . . , WLm1˜WLmn, and the plurality of ground selection lines GSL1,GSL2, . . . , GSLm. The drive line to which the reference line REF_LN iscoupled may not have a defect such that a substantial leakage currentmay not flow from the drive line. The nonvolatile memory device 20 maycharge the test line TEST_LN and the reference line REF_LN to the samevoltage level. After that, the nonvolatile memory device 20 may generatethe test result signal TEST_RE, which indicates whether a leakagecurrent flows from the test line TEST_LN, by comparing a decrease amountof the voltage V_TEST_ND of the test node TEST_ND, which may be causedby a leakage current flowing from the test line TEST_LN or aself-discharge of the test line TEST_LN, with a decrease amount of thevoltage V_REF_ND of the reference node REF_ND, which may be caused by aself-discharge of the reference line REF_LN.

Therefore, the nonvolatile memory device 20 including the leakagecurrent detection device 10 according to example embodiments mayeffectively detect a leakage current flowing from the plurality ofstring selection lines SSL1, SSL2, . . . , SSLm, the plurality of wordlines WL11˜WL1 n, WL21˜WL2 n, . . . , WLm1˜WLmn, and the plurality ofground selection lines GSL1, GSL2, . . . , GSLm.

FIG. 9 is a block diagram illustrating a nonvolatile memory deviceaccording to example embodiments. Referring to FIG. 9, a nonvolatilememory device 30 may include a memory cell array 500, an address decoder601, a controller 701, a data I/O circuit 800, a voltage generator 850,and a leakage current detection device 10. The memory cell array 500included in the nonvolatile memory device 30 of FIG. 9 may be the sameas the memory cell array 500 included in the nonvolatile memory device20 of FIG. 5.

The controller 701 may control overall operations of the nonvolatilememory device 30 based on a command signal CMD and an address signalADDR received from an external device such as a memory controller. Forexample, the controller 701 may control a program operation, a readoperation, the erase operation, and a leakage test operation of thenonvolatile memory device 30 based on the command signal CMD and theaddress signal ADDR.

In some example embodiments, the controller 701 may include a normalline table NLT 710, which stores addresses of normal lines, from which asubstantial leakage current does not flow, among the plurality of stringselection lines SSL1, SSL2, . . . , SSLm, the plurality of word linesWL11˜WL1 n, WL21˜WL2 n, . . . , WLm1˜WLmn, and the plurality of groundselection lines GSL1, GSL2, . . . , GSLm. When the controller 701receives the command signal CMD that does not correspond to a leakagetest command, the controller 701 may provide a test enable signal T_ENin a deactivated state to the address decoder 601. In this case, thecontroller 701 may generate a row address RADDR and a column addressCADDR based on the address signal ADDR. The controller 701 may providethe row address RADDR to the address decoder 601, and provide the columnaddress CADDR (not shown) to the data I/O circuit 800.

The voltage generator 850 may generate various voltages required foroperations of the nonvolatile memory device 30, and provide the variousvoltages to the address decoder 601. For example, the voltage generator850 may generate a program voltage, a pass voltage and a verificationvoltage that are used in the program operation, generate a read voltagethat is used in the read operation, and generate an erase voltage thatis used in the erase operation.

The address decoder 601 may be connected to the memory cell array 500through the plurality of string selection lines SSL1, SSL2, . . . ,SSLm, the plurality of word lines WL11˜WL1 n, WL21˜WL2 n, . . . ,WLm1˜WLmn, the plurality of ground selection lines GSL1, GSL2, . . . ,GSLm, and the plurality of common source lines CSL1, CSL2, . . . , CSLm.When the address decoder 601 receives the test enable signal T_EN in thedeactivated state, the address decoder 601 may select one of theplurality of word lines WL11˜WL1 n, WL21˜WL2 n, . . . , WLm1˜WLmn basedon the row address RADDR received from the controller 701, and providethe various voltages received from the voltage generator 850 to theselected word line and the unselected word lines.

The data I/O circuit 800 may be connected to the memory cell array 500through the plurality of bit lines BL1, BL2, . . . , BLz. The data I/Ocircuit 800 may select at least one of the plurality of bit lines BL1,BL2, . . . , BLz based on the column address CADDR received from thecontroller 701, output data DATA read from a memory cell connected tothe selected at least one bit line to an external device, and write dataDATA received from the external device in a memory cell connected to theselected at least one bit line.

In some example embodiments, the data I/O circuit 800 may include asense amplifier, a page buffer, a column selection circuit, a writedriver, a data buffer, etc.

Alternately, when the controller 701 receives the command signal CMDthat corresponds to the leakage test command, the controller 701 mayprovide the test enable signal T_EN in an activated state to the addressdecoder 601. In this case, the controller 701 may generate a test lineselection signal TLSS and a reference line selection signal RLSS basedon the address signal ADDR, and provide the test line selection signalTLSS and the reference line selection signal RLSS to the address decoder601.

For example, the controller 701 may generate the test line selectionsignal TLSS indicating one of the plurality of string selection linesSSL1, SSL2, . . . , SSLm, the plurality of word lines WL11˜WL1 n,WL21˜WL2 n, . . . , WLm1˜WLmn, and the plurality of ground selectionlines GSL1, GSL2, . . . , GSLm that is represented by the address signalADDR. In addition, when the address signal ADDR represents one of theplurality of string selection lines SSL1, SSL2, . . . , SSLm, thecontroller 701 may generate the reference line selection signal RLSScorresponding to an address of a string selection line among theaddresses of the normal lines stored in the normal line table 710. Whenthe address signal ADDR represents one of the plurality of word linesWL11˜WL1 n, WL21˜WL2 n, . . . , WLm1˜WLmn, the controller 701 maygenerate the reference line selection signal RLSS corresponding to anaddress of a word line among the addresses of the normal lines stored inthe normal line table 710. When the address signal ADDR represents oneof the plurality of ground selection lines GSL1, GSL2, . . . , GSLm, thecontroller 701 may generate the reference line selection signal RLSScorresponding to an address of a ground selection line among theaddresses of the normal lines stored in the normal line table 710.

When the address decoder 601 receives the test enable signal T_EN in theactivated state, the address decoder 601 may connect a test line TEST_LNto one of the plurality of string selection lines SSL1, SSL2, . . . ,SSLm, the plurality of word lines WL11˜WL1 n, WL21˜WL2 n, . . . ,WLm1˜WLmn, and the plurality of ground selection lines GSL1, GSL2, . . ., GSLm based on the test line selection signal TLSS, and connect areference line REF_LN to another one of the plurality of stringselection lines SSL1, SSL2, . . . , SSLm, the plurality of word linesWL11˜WL1 n, WL21˜WL2 n, . . . , WLm1˜WLmn, and the plurality of groundselection lines GSL1, GSL2, . . . , GSLm based on the reference lineselection signal RLSS.

The leakage current detection device 10 included in the nonvolatilememory device 30 of FIG. 9 may be the same as the leakage currentdetection device 10 included in the nonvolatile memory device 20 of FIG.5. Therefore, when the nonvolatile memory device 30 including theleakage current detection device 10 receives the command signal CMDcorresponding to the leakage test command from an external device suchas a memory controller, the nonvolatile memory device 30 may perform aleakage test on one of the plurality of string selection lines SSL1,SSL2, . . . , SSLm, the plurality of word lines WL11˜WL1 n, WL21˜WL2 n,. . . , WLm1˜WLmn, and the plurality of ground selection lines GSL1,GSL2, . . . , GSLm that is represented by the address signal ADDR, andprovide a test result signal TEST_RE to the memory controller.

Therefore, the memory controller may effectively determine whether aleakage current flows from a drive line corresponding to the addresssignal ADDR based on the test result signal TEST_RE. When the memorycontroller determines that a leakage current flows from the drive linecorresponding to the address signal ADDR, the memory controller mayconsider a memory block, which is coupled to the drive linecorresponding to the address signal ADDR among plurality of memoryblocks 510-1, 510-2, . . . , 510-m, as a bad memory block. After that,the memory controller may not use the bad memory block as a storagemedium.

FIG. 10 is a flow chart illustrating a method of detecting a leakagecurrent in a nonvolatile memory device according to example embodiments.In FIG. 10, a method of detecting a leakage current flowing from a driveline coupled to a memory cell array of the nonvolatile memory device isrepresented. Referring to FIG. 10, a test line, which is coupled to afirst drive line among drive lines coupled to a memory cell array of anonvolatile memory device, and a reference line, which is coupled to asecond drive line among the drive lines coupled to the memory cell arrayof the nonvolatile memory device, are charged to a same voltage (stepS100). The first drive line and the second drive line deliver a sametype of a drive signal to the memory cell array.

In some example embodiments, a supply voltage may be provided to a testnode, which is coupled to the test line through a first transmissiontransistor, and a reference node, which is coupled to the reference linethrough a second transmission transistor, and the first transmissiontransistor and the second transmission transistor may be turned on tocharge the test line and the reference line to the same voltage level.

In some example embodiments, each of the test line and the referenceline may correspond to a word line delivering a word line signal to thememory cell array of the nonvolatile memory device. In some exampleembodiments, each of the test line and the reference line may correspondto a string selection line delivering a string selection signal to thememory cell array of the nonvolatile memory device. In some exampleembodiments, each of the test line and the reference line may correspondto a ground selection line delivering a ground selection signal to thememory cell array of the nonvolatile memory device.

The second drive line, which is coupled to the reference line, may nothave a defect such that a substantial leakage current may not flow fromthe second drive line.

After that, the test line and the reference line are floated (stepS200).

In some example embodiments, the test node and the reference node may bedisconnected from the supply voltage while the first transmissiontransistor and the second transmission transistor are turned on suchthat the test line and the reference line may be floated. A test resultsignal, which indicates whether a leakage current flows from the testline, is generated based on a voltage of the test line and a voltage ofthe reference line after a detection time from a time at which the testline and the detection node are floated (step S300).

In some example embodiments, a logic level of the test result signal maybe changed when a voltage of the test node is lower than a voltage ofthe reference node by a predetermined voltage after the detection timefrom a time at which the test node and the reference node aredisconnected from the supply voltage. The method of detecting a leakagecurrent in a nonvolatile memory device illustrated in FIG. 10 may beperformed by the nonvolatile memory device 20 of FIG. 5 or thenonvolatile memory device 30 of FIG. 9.

FIG. 11 is a block diagram illustrating a memory system according toexample embodiments. Referring to FIG. 11, a memory system 900 includesa memory controller 910 and a nonvolatile memory device 920. Thenonvolatile memory device 920 includes a memory cell array 921, aleakage current detection device 922 and a data I/O circuit 923. Thememory cell array 921 may include a plurality of memory blocks. Theplurality of memory blocks may be coupled to the leakage currentdetection device 922 through a plurality of string selection lines SSL,a plurality of word lines WL, and a plurality of ground selection linesGSL.

The leakage current detection device 922 may select one of the pluralityof string selection lines SSL, the plurality of word lines WL, and theplurality of ground selection lines GSL as a test line, and selectanother one of the plurality of string selection lines SSL, theplurality of word lines WL, and the plurality of ground selection linesGSL as a reference line. The reference line may be of the same type asthe test line. A substantial leakage current may not flow from thereference line. The leakage current detection device 922 may charge thetest line and the reference line to the same voltage level. After that,the leakage current detection device 922 may float the test line and thereference line. The leakage current detection device 922 may generate atest result signal TEST_RE, which indicates whether a leakage currentflows from the test line, based on a change of a voltage of the testline and a change of a voltage of the reference line, and provide thetest result signal TEST_RE to the memory controller 910.

The data I/O circuit 923 may be connected to the memory cell array 921through a plurality of bit lines. The data I/O circuit 923 may select atleast one of the plurality of bit lines, output data read from a memorycell connected to the selected at least one bit line to the memorycontroller 910, and write data received from the memory controller 910in a memory cell connected to the selected at least one bit line.

The nonvolatile memory device 920 may be implemented with thenonvolatile memory device 20 of FIG. 5 or the nonvolatile memory device30 of FIG. 9. The memory controller 910 may control the nonvolatilememory device 920. The memory controller 910 may control data transferbetween an external host and the nonvolatile memory device 920. Thememory controller 910 may include a central processing unit CPU 911, abuffer memory RAM 912, a host interface 913 and a memory interface 914.

The central processing unit 911 may perform operations for the datatransfer. The buffer memory 912 may be implemented by a dynamic randomaccess memory (DRAM), a static random access memory (SRAM), a phasechange random access memory (PRAM), a ferroelectric random access memory(FRAM), a resistance random access memory (RRAM), a magnetic randomaccess memory (MRAM), etc. The buffer memory 912 may be an operationalmemory of the central processing unit 911. In some example embodiments,the buffer memory 912 may be included in the memory controller 910. Inother example embodiments, the buffer memory 912 may be outside of thememory controller 910.

The host interface 913 may be coupled to the host, and the memoryinterface 914 may be coupled to the nonvolatile memory device 920. Thecentral processing unit 911 may communicate with the host via the hostinterface 913. For example, the host interface 913 may be configured tocommunicate with the host using at least one of various interfaceprotocols, such as a universal serial bus (USB), a multimedia card(MMC), a peripheral component interconnect-express (PCI-E), a smallcomputer system interface (SCSI), a serial-attached SCSI (SAS), a serialadvanced technology attachment (SATA), a parallel advanced technologyattachment (PATA), an enhanced small disk interface (ESDI), integrateddrive electronics (IDE), and so on. Further, the central processing unit911 may communicate with the nonvolatile memory device 920 via thememory interface 914.

In some example embodiments, the memory controller 910 may furtherinclude an error correction code (ECC) block 915 for error correction.In some example embodiments, the memory controller 910 may be built inthe nonvolatile memory device 920, or the memory controller 910 and thenonvolatile memory device 920 may be implemented as separate chips. Thememory system 900 may be implemented as a memory card, a solid statedrive, and so on.

FIG. 12 is a block diagram illustrating a memory card according toexample embodiments. Referring to FIG. 12, a memory card 1000 includes aplurality of connecting pins 1010, a memory controller 1020 and anonvolatile memory device 1030. The connecting pins 1010 may be coupledto an external host to transfer signals between the host and the memorycard 1000. The connecting pins 1010 may include a clock pin, a commandpin, a data pin and/or a reset pin. The memory controller 1020 mayreceive data from the host, and may store the received data in thenonvolatile memory device 1030.

A memory cell array included in the nonvolatile memory device 1030 mayinclude a plurality of memory blocks coupled to a plurality of stringselection lines, a plurality of word lines, and a plurality of groundselection lines. The nonvolatile memory device 1030 may select one ofthe plurality of string selection lines, the plurality of word lines,and the plurality of ground selection lines as a test line, and selectanother one of the plurality of string selection lines, the plurality ofword lines, and the plurality of ground selection lines as a referenceline. The reference line may be of the same type as the test line. Asubstantial leakage current may not flow from the reference line. Thenonvolatile memory device 1030 may charge the test line and thereference line to the same voltage level. After that, the nonvolatilememory device 1030 may float the test line and the reference line. Thenonvolatile memory device 1030 may generate a test result signal, whichindicates whether a leakage current flows from the test line, based on achange of a voltage of the test line and a change of a voltage of thereference line.

The nonvolatile memory device 1030 may be implemented with thenonvolatile memory device 20 of FIG. 5 or the nonvolatile memory device30 of FIG. 9. The memory card 1000 may include a MMC, an embedded MMC(eMMC), a hybrid embedded MMC (hybrid eMMC), a secure digital (SD) card,a micro-SD card, a memory stick, an ID card, a personal computer memorycard international association (PCMCIA) card, a chip card, a USB card, asmart card, a compact flash (CF) card, and so on. In some exampleembodiments, the memory card 1000 may be coupled to the host, such as adesktop computer, a laptop computer, a tablet computer, a mobile phone,a smart phone, a music player, a personal digital assistants (PDA), aportable multimedia player (PMP), a digital television, a digitalcamera, a portable game console, and so on.

FIG. 13 is a block diagram illustrating a solid state drive (SSD) systemaccording to example embodiments. Referring to FIG. 13, a SSD system2000 includes a host 2100 and a SSD 2200. The SSD 2200 may include firstthrough n-th nonvolatile memory devices 2210-1, 2210-2, . . . , 2210-nand a SSD controller 2220. The first through n-th nonvolatile memorydevices 2210-1, 2210-2, . . . , 2210-n may be used as a storage mediumof the SSD 2200.

A memory cell array included in each of the first through n-thnonvolatile memory devices 2210-1, 2210-2, . . . , 2210-n may include aplurality of memory blocks coupled to a plurality of string selectionlines, a plurality of word lines, and a plurality of ground selectionlines. Each of the first through n-th nonvolatile memory devices 2210-1,2210-2, . . . , 2210-n may select one of the plurality of stringselection lines, the plurality of word lines, and the plurality ofground selection lines as a test line, and select another one of theplurality of string selection lines, the plurality of word lines, andthe plurality of ground selection lines as a reference line. Thereference line may be of the same type as the test line. A substantialleakage current may not flow from the reference line. Each of the firstthrough n-th nonvolatile memory devices 2210-1, 2210-2, . . . , 2210-nmay charge the test line and the reference line to the same voltagelevel. After that, each of the first through n-th nonvolatile memorydevices 2210-1, 2210-2, . . . , 2210-n may float the test line and thereference line. Each of the first through n-th nonvolatile memorydevices 2210-1, 2210-2, . . . , 2210-n may generate a test resultsignal, which indicates whether a leakage current flows from the testline, based on a change of a voltage of the test line and a change of avoltage of the reference line.

Each of the first through n-th nonvolatile memory devices 2210-1,2210-2, . . . , 2210-n may be implemented with the nonvolatile memorydevice 20 of FIG. 5 or the nonvolatile memory device 30 of FIG. 9. TheSSD controller 2220 may be coupled to the first through n-th nonvolatilememory devices 2210-1, 2210-2, . . . , 2210-n by first through n-thchannels CH1, CH2, . . . , CHn, respectively. The SSD controller 2220may exchange a signal SGL with the host 2100 through a signal connector2221. The signal SGL may include a command, an address and data. The SSDcontroller 2220 may perform a program operation and a read operation onthe first through n-th nonvolatile memory devices 2210-1, 2210-2, . . ., 2210-n according to the command received from the host 2100.

The SSD 2200 may further include an auxiliary power supply 2230. Theauxiliary power supply 2230 may receive power PWR from the host 2100through a power connector 2231 and provide power to the SSD controller2220. The auxiliary power supply 2230 may be placed inside or outsidethe SSD 2200. For example, the auxiliary power supply 2230 may be placedin a main board and provide auxiliary power to the SSD 2200.

FIG. 14 is a block diagram illustrating a mobile system according toexample embodiments. Referring to FIG. 14, a mobile system 3000 includesan application processor AP 3100, a connectivity unit 3200, a userinterface 3300, a nonvolatile memory device NVM 3400, a volatile memorydevice VM 3500 and a power supply 3600. In some embodiments, the mobilesystem 3000 may be a mobile phone, a smart phone, a personal digitalassistant (PDA), a portable multimedia player (PMP), a digital camera, amusic player, a portable game console, a navigation system, etc.

The application processor 3100 may execute applications, such as a webbrowser, a game application, a video player, etc. In some exampleembodiments, the application processor 3100 may include a single core ormultiple cores. For example, the application processor 3100 may be amulti-core processor, such as a dual-core processor, a quad-coreprocessor, a hexa-core processor, etc. The application processor 3100may include an internal or external cache memory.

The connectivity unit 3200 may perform wired or wireless communicationwith an external device. For example, the connectivity unit 3200 mayperform Ethernet communication, near field communication (NFC), radiofrequency identification (RFID) communication, mobile telecommunication,memory card communication, universal serial bus (USB) communication,etc. In some embodiments, the connectivity unit 3200 may include abaseband chipset that supports communications, such as global system formobile communications (GSM), general packet radio service (GPRS),wideband code division multiple access (WCDMA), high speeddownlink/uplink packet access (HSxPA), etc.

The nonvolatile memory device 3400 may store a boot image for bootingthe mobile system 3000. A memory cell array included in the nonvolatilememory device 3400 may include a plurality of memory blocks coupled to aplurality of string selection lines, a plurality of word lines, and aplurality of ground selection lines. The nonvolatile memory device 3400may select one of the plurality of string selection lines, the pluralityof word lines, and the plurality of ground selection lines as a testline, and select another one of the plurality of string selection lines,the plurality of word lines, and the plurality of ground selection linesas a reference line. The reference line may be of the same type as thetest line. A substantial leakage current may not flow from the referenceline. The nonvolatile memory device 3400 may charge the test line andthe reference line to the same voltage level. After that, thenonvolatile memory device 3400 may float the test line and the referenceline. The nonvolatile memory device 3400 may generate a test resultsignal, which indicates whether a leakage current flows from the testline, based on a change of a voltage of the test line and a change of avoltage of the reference line.

The nonvolatile memory device 3400 may be implemented with thenonvolatile memory device 20 of FIG. 5 or the nonvolatile memory device30 of FIG. 9. The volatile memory device 3500 may store data processedby the application processor 3100, or may operate as a working memory.The user interface 3300 may include at least one input device, such as akeypad, a touch screen, etc., and at least one output device, such as aspeaker, a display device, etc. The power supply 3600 may supply a powersupply voltage to the mobile system 3000.

In some embodiments, the mobile system 3000 may further include an imageprocessor, and/or a storage device, such as a memory card, a solid statedrive (SSD), a hard disk drive (HDD), a CD-ROM, etc. In someembodiments, the mobile system 3000 and/or components of the mobilesystem 3000 may be packaged in various forms, such as package on package(PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plasticleaded chip carrier (PLCC), plastic dual in-line package (PDIP), die inwaffle pack, die in wafer form, chip on board (COB), ceramic dualin-line package (CERDIP), plastic metric quad flat pack (MQFP), thinquad flat pack (TQFP), small outline IC (SOIC), shrink small outlinepackage (SSOP), thin small outline package (TSOP), system in package(SIP), multi chip package (MCP), wafer-level fabricated package (WFP),or wafer-level processed stack package (WSP).

The foregoing is illustrative of the present inventive concept and isnot to be construed as limiting thereof. Although a few exampleembodiments have been described, those skilled in the art will readilyappreciate that many modifications are possible in the exampleembodiments without materially departing from the novel teachings andadvantages of the present inventive concept. Accordingly, all suchmodifications are intended to be included within the scope of thepresent inventive concept as defined in the claims. Therefore, it is tobe understood that the foregoing is illustrative of various exampleembodiments and is not to be construed as limited to the specificexample embodiments disclosed, and that modifications to the disclosedexample embodiments, as well as other example embodiments, are intendedto be included within the scope of the appended claims.

What is claimed is:
 1. A leakage current detection device for anonvolatile memory device having a memory cell array coupled to drivelines, the leakage current detection device comprising: a test detectioncircuit coupled between a test node and a test line, the test linecorresponding to a first drive line from among the drive lines coupledto the memory cell array of the nonvolatile memory device, the testdetection circuit configured to provide a supply voltage to the testnode to charge the test line, to float the test node and the test line,and to decrease a voltage of the test node based on a leakage currentflowing from the test line; a reference detection circuit coupledbetween a reference node and a reference line, the reference linecorresponding to a second drive line from among the drive lines that iscoupled to the memory cell array of the nonvolatile memory device andthat is configured to deliver a drive signal of a type that is the sameas a type of a drive signal delivered by the first drive line, thereference detection circuit configured to provide the supply voltage tothe reference node to charge the reference line, to float the referencenode and the reference line, and to decrease a voltage of the referencenode based on a self-discharge of the reference line; a comparatorconfigured to output a comparison signal by comparing the voltage of thetest node with the voltage of the reference node; and a latch circuitconfigured to latch the comparison signal in response to a latch controlsignal, and to output the latched comparison signal as a test resultsignal, wherein the comparator is configured to change a logic level ofthe comparison signal when the voltage of the test node becomes lowerthan the voltage of the reference node by a predetermined voltage. 2.The leakage current detection device of claim 1, wherein the testdetection circuit comprises: a first charge transistor coupled betweenthe supply voltage and the test node, the first charge transistorincluding a gate configured to receive a charge control signal; a firstenable transistor coupled between the test node and a ground voltage,the first enable transistor including a gate configured to receive anenable signal; and a first transmission transistor coupled between thetest line and the test node, the first transmission transistor includinga gate configured to receive a transmission control signal.
 3. Theleakage current detection device of claim 2, wherein the referencedetection circuit comprises: a second charge transistor coupled betweenthe supply voltage and the reference node, the second charge transistorincluding a gate configured to receive the charge control signal; asecond enable transistor coupled between the reference node and theground voltage, the second enable transistor including a gate configuredto receive the enable signal; and a second transmission transistorcoupled between the reference line and the reference node, the secondtransmission transistor including a gate configured to receive thetransmission control signal.
 4. The leakage current detection device ofclaim 3, further comprising: a control circuit configured to turn offthe first enable transistor and the second enable transistor using theenable signal, turn on the first charge transistor and the second chargetransistor using the charge control signal, and turn on the firsttransmission transistor and the second transmission transistor using thetransmission control signal at a first time, turn off the first chargetransistor and the second charge transistor using the charge controlsignal to float the test node and the reference node at a second time,and provide the latch control signal to the latch circuit at a thirdtime, wherein a time duration between the second time and the third timecorresponds to a detection time.
 5. The leakage current detection deviceof claim 4, wherein the control circuit is configured to adjust avoltage level of the transmission control signal in a logic high statebased on the type of the drive signal delivered by the test line and thetype of the drive signal delivered by the reference line.
 6. The leakagecurrent detection device of claim 4, wherein the control circuit isconfigured to adjust a length of the detection time based on a magnitudeof a leakage current of the test line to be detected.
 7. The leakagecurrent detection device of claim 1, wherein the test line and thereference line respectively correspond to word lines coupled to thememory cell array of the nonvolatile memory device.
 8. The leakagecurrent detection device of claim 1, wherein the test line and thereference line respectively correspond to string selection lines coupledto the memory cell array of the nonvolatile memory device.
 9. Theleakage current detection device of claim 1, wherein the test line andthe reference line respectively correspond to ground selection linescoupled to the memory cell array of the nonvolatile memory device.
 10. Anonvolatile memory device, comprising: a memory cell array including aplurality of memory cell blocks; a line selection circuit coupled to theplurality of memory cell blocks through a plurality of string selectionlines, a plurality of word lines, and a plurality of ground selectionlines, the line selection circuit being configured to couple a test lineto one of the plurality of string selection lines, the plurality of wordlines, and the plurality of ground selection lines based on a test lineselection signal, and to couple a reference line to another one of theplurality of string selection lines, the plurality of word lines, andthe plurality of ground selection lines based on a reference lineselection signal; a leakage current detection device configured tocharge the test line and the reference line to a same voltage, to floatthe test line and the reference line, and to generate a test resultsignal, which indicates whether a leakage current flows from the testline, based on a change of a voltage of the test line and a change of avoltage of the reference line; and a controller configured to generatethe test line selection signal and the reference line selection signal,wherein the controller is further configured to store addresses ofnormal lines from among the plurality of string selection lines, theplurality of word lines and the plurality of ground selection lines, andgenerate the reference line selection signal corresponding to an addressfrom among the stored addresses of the normal lines.
 11. The nonvolatilememory device of claim 10, wherein the leakage current detection devicecomprises: a test detection circuit coupled between a test node and thetest line, the test detection circuit being configured to provide asupply voltage to the test node to charge the test line, to float thetest node and the test line, and to decrease a voltage of the test nodebased on the leakage current flowing from the test line; a referencedetection circuit coupled between a reference node and the referenceline, the reference detection circuit being configured to provide thesupply voltage to the reference node to charge the reference line, tofloat the reference node and the reference line, and to decrease avoltage of the reference node based on a self-discharge of the referenceline; a comparator configured to output a comparison signal by comparingthe voltage of the test node with the voltage of the reference node; anda latch circuit configured to latch the comparison signal in response toa latch control signal, and to output the latched comparison signal asthe test result signal.
 12. The nonvolatile memory device of claim 11,wherein the test detection circuit comprises: a first charge transistorcoupled between the supply voltage and the test node, the first chargetransistor including a gate configured to receive a charge controlsignal; a first enable transistor coupled between the test node and aground voltage, the first enable transistor including a gate configuredto receive an enable signal; and a first transmission transistor coupledbetween the test line and the test node, the first transmissiontransistor including a gate configured to receive a transmission controlsignal; and wherein the reference detection circuit comprises a secondcharge transistor coupled between the supply voltage and the referencenode, the second charge transistor including a gate configured toreceive the charge control signal; a second enable transistor coupledbetween the reference node and the ground voltage, the second enabletransistor including a gate configured to receive the enable signal; anda second transmission transistor coupled between the reference line andthe reference node, the second transmission transistor including a gateconfigured to receive the transmission control signal.
 13. Thenonvolatile memory device of claim 10, wherein: when the test line iscoupled to one of the plurality of word lines, the reference line iscoupled to another one of the plurality of word lines; when the testline is coupled to one of the plurality of string selection lines, thereference line is coupled to another one of the plurality of stringselection lines; and when the test line is coupled to one of theplurality of ground selection lines, the reference line is coupled toanother one of the plurality of ground selection lines.
 14. Thenonvolatile memory device of claim 10, wherein the memory cell arraycorresponds to a three-dimensional memory array.
 15. A method of leakagecurrent detection for a nonvolatile memory device having a memory cellarray coupled to drive lines, the method comprising: coupling a testdetection circuit between a test node and a test line, the test linecorresponding to a first drive line from among the drive lines coupledto the memory cell array of the nonvolatile memory device, the testdetection circuit providing a supply voltage to the test node to chargethe test line, floating the test node and the test line, and decreasinga voltage of the test node based on a leakage current flowing from thetest line; coupling a reference detection circuit between a referencenode and a reference line, the reference line corresponding to a seconddrive line from among the drive lines that is coupled to the memory cellarray of the nonvolatile memory device and that is configured to delivera drive signal of a type that is the same as a type of a drive signaldelivered by the first drive line, the reference detection circuitproviding the supply voltage to the reference node to charge thereference line, floating the reference node and the reference line, anddecreasing a voltage of the reference node based on a self-discharge ofthe reference line; outputting a comparison signal by comparing thevoltage of the test node with the voltage of the reference node, a logiclevel of the comparison signal changing when the voltage of the testnode becomes lower than the voltage of the reference node by apredetermined voltage; and latching the comparison signal in response toa latch control signal, and outputting the latched comparison signal asa test result signal.
 16. The method of claim 15, wherein coupling thetest detection circuit comprises: coupling a first charge transistorbetween the supply voltage and the test node, the first chargetransistor including a gate to receive a charge control signal; couplinga first enable transistor between the test node and a ground voltage,the first enable transistor including a gate to receive an enablesignal; and coupling a first transmission transistor between the testline and the test node, the first transmission transistor including agate to receive a transmission control signal.
 17. The method of claim16, wherein coupling the reference detection circuit comprises: couplinga second charge transistor between the supply voltage and the referencenode, the second charge transistor including a gate to receive thecharge control signal; coupling a second enable transistor between thereference node and the ground voltage, the second enable transistorincluding a gate to receive the enable signal; and coupling a secondtransmission transistor between the reference line and the referencenode, the second transmission transistor including a gate to receive thetransmission control signal.
 18. The method of claim 17, furthercomprising: turning off the first enable transistor and the secondenable transistor using the enable signal, turning on the first chargetransistor and the second charge transistor using the charge controlsignal, and turning on the first transmission transistor and the secondtransmission transistor using the transmission control signal at a firsttime; turning off the first charge transistor and the second chargetransistor using the charge control signal to float the test node andthe reference node at a second time; and providing the latch controlsignal at a third time; wherein a time duration between the second timeand the third time corresponds to a detection time.
 19. The method ofclaim 18, wherein the voltage level of the transmission control signalis adjusted in a logic high state based on the type of the drive signaldelivered by the test line and the type of the drive signal delivered bythe reference line.